1. Field of the Invention
The present invention relates to a memory device and a method of operating such a memory device in a speculative read mode.
2. Description of the Prior Art
As process geometries shrink in modern data processing systems, the variability in the operating characteristics of the individual circuit elements increases. Considering as an example a memory device consisting of an array of memory cells, it will be understood that each memory cell will typically consist of a number of electronic components such as transistors, and the variability in those individual components significantly increases as process geometries shrink. Furthermore, there is an increasing desire to operate data processing systems at lower and lower supply voltages, and as the supply voltage decreases, reliability issues due to the variations in the individual components become more prominent.
In order to ensure correct operation of a memory, memory system designers normally operate the memory system to sample a read value therefrom at a time chosen to ensure that the correct read value will have been driven out from the memory given a worst case set of assumptions surrounding manufacturing variation, ambient conditions, etc associated with the memory system concerned. Hence, a memory system designer will calculate a slowest likely read speed and then add a certain safety margin to this when deciding at what speed the memory should be operated. Whilst this approach is safe in terms of ensuring correct operation and data integrity, it can significantly limit the data processing performance that may be achieved.
Furthermore, given the increase in variability of components that occurs as process geometries shrink, this will then lead to larger margins needing to be specified in order to ensure correct operation.
With the aim of seeking to remove worst case safety margins, ARM Limited developed an in-situ error detection and correction technique often referred to as Razor. The basic Razor technique is described in U.S. Pat. No. 7,278,080, the entire contents of which are hereby incorporated by reference. In accordance with the basic Razor technique, errors are detected in processing stages by comparison of a non-delayed data value with a delayed data value, these data values being captured at slightly different times. In the event of a difference in the data values compared, this indicates an error condition, and the error can be corrected in-situ. By incorporation of such techniques, it is then possible to reduce the safety margins within a design, since it is possible to cope with a small non-zero error rate in the data due to the ability of the Razor mechanism to protect and correct such errors in-situ.
Returning to the particular issue of reading data from a memory device, the individual memory cells are typically connected to a pair of bit lines, and during a read operation, one of the bit lines coupled to an addressed memory cell will discharge whilst the other remains at a precharged logic level, which bit line discharges being dependent on the data value stored within the addressed memory cell. Sense amplifier circuitry can then be used to detect the differential signals developing on the pair of bit lines for each addressed memory cell in order to determine the data value stored in each addressed memory cell. To ensure correct operation, the memory system designer needs to allow a read time to elapse before the sense amplifier circuitry is triggered to sense the signals on the bit lines, and typically that read time will be set long enough to ensure that in the worst case conditions the differential signals on the bit lines will have developed to a sufficient extent to ensure correct sensing of the data values by the sense amplifier circuitry. Hence, purely by way of illustration, it may be necessary for there to be at least 100 mV of potential difference between the signals on the pair of bit lines before it can be guaranteed that a sense amplifier will correctly detect the data value stored in the addressed memory cell connected to those bit lines.
However, it will be appreciated that by setting the read time so as to account for the worst case conditions, this can significantly impact the speed of operation of the memory device, since in many situations it would have been possible to have read the data earlier due to the differential signals developing more quickly than in the worst case scenario.
With the above issue in mind, commonly owned U.S. Pat. No. 7,260,001, the entire contents of which are hereby incorporated by reference, describes a Razor-style approach for performing a read operation within a memory device. In accordance with the technique described therein, both a fast data reading mechanism and a slow data reading mechanism are provided, in one embodiment both data reading mechanisms being formed by sense amplifier circuits. The fast data reading mechanism is arranged to read a data value from the memory in order to generate a fast read result that is output from the memory for further processing, whilst the slow data reading mechanism reads the data value from said memory to generate a slow read result available after the fast read result has been output for further processing, the slow data reading mechanism being less prone to error in reading the data value than the fast data reading mechanism. The fast read result and the slow read result are then compared to detect if the fast read result differs from the slow read result, and error repair logic is then used if the results differ in order to suppress any further processing based on the fast read result. In that scenario, the slow read result is then typically output in place of the fast read result with the further processing then being restarted based upon the slow read result.
Whilst such an approach can improve performance of the memory device by reducing the margins that are incorporated when setting the read time, it can give rise to a number of problems. In particular, since the voltage on the bit lines need to be sensed at two different times, the bit lines cannot begin to be precharged for the next read operation until both the fast data reading mechanism and the slow data reading mechanism have sampled the data on the bit lines, and accordingly this limits the operating speed of the memory device. This also adversely affects power consumption, since the bit lines are discharged to a lower point by the time the slow data reading mechanism has sampled the data, and accordingly more power is consumed in each precharge operation. In addition, due to the need to resample the data via the slow data reading mechanism, various disturbance effects can arise. As one example, there will be leakage within each column of bit lines from the non-addressed memory cells connected to that column, such that after a period of time the bit line that is not discharging due to the contents of the addressed memory cell does in any event start to lose voltage due to leakage current, thereby giving rise to an accuracy problem in detection of the data by the slow data reading mechanism. Further, such leakage also increases power consumption.
Accordingly, it would be desirable to provide an improved technique for increasing the performance of read operations within a memory device.